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[VHDL-FPGA-Verilog] TankWar

Description: 使用Verilog语言在ise平台上实现的坦克大战游戏，实现了基本的游戏功能(The use of Verilog language in the ISE platform to achieve the tank war game, to achieve the basic functions of the game)
Platform: | Size: 32106496 | Author: 日日夜夜 | Hits:

[Other] 何宾EDK

Description: 何老师的FPGA软核设计，xilinx ise(Mr. Ho's FPGA soft core design, Xilinx ISE)
Platform: | Size: 10105856 | Author: huhotto | Hits:

[VHDL-FPGA-Verilog] clock

Description: FPGA时钟功能，具备修改时间，闹钟等功能，适合初学者，本人初学时自己写的(just lke the chinese says)
Platform: | Size: 311296 | Author: yhhyhh | Hits:

[VHDL-FPGA-Verilog] traffic_lab6

Description: 使用FPGA实现交通上的红绿灯功能，主要是为了学习灵活运用FPGA上的定时功能(just like the chinese say,my english is poor)
Platform: | Size: 3080192 | Author: yhhyhh | Hits:

[VHDL-FPGA-Verilog] VGA_test3

Description: 利用FPGA实现VGA的驱动，驱动VGA进行工作并通过该功能在显示器上显示一定的内容(my english is poor, so have a look at the chinese)
Platform: | Size: 1643520 | Author: yhhyhh | Hits:

[Other] Multiplier

Description: fpga门电路实现的8位乘法器, verilog 语言编写，ise平台(implementation of multipler)
Platform: | Size: 134144 | Author: piupiujiang | Hits:

[VHDL-FPGA-Verilog] Half-Adder

Description: This is an example to implement an Half-adder for xilinx FPGA
Platform: | Size: 21504 | Author: DanCerv | Hits:

[VHDL-FPGA-Verilog] parallel_norflash_test

Description: ISE工程，并行nor flash的读、写、擦出，其中有个调用FIFO16-16的IP核，已经在工程中(ISE engineering, parallel nor FLASH read, write, erase, where there is a call FIFO16-16 IP core, has been in the project)
Platform: | Size: 1124352 | Author: 张超 | Hits:

[Communication-Mobile] RISC_CPU完整代码

Description: 硬件实现一个完整的CPU，利用verilog编写，可在ISE上直接使用(Hardware implements a full CPU)
Platform: | Size: 3099648 | Author: TJUWUCK | Hits:

[Other] i2s_top

Description: i2s接口fpga实现，工作在主模式，ISE和vivado下已验证(I2S interface FPGA implementation, working in the master mode)
Platform: | Size: 2048 | Author: blink_liao | Hits:

[VHDL-FPGA-Verilog] eeprom_test_Verilog

Description: eeprom工程，实现了基本的读写，供参考。工程使用的IDE为“ISE Design Suite 14.7”，使用时可根据自己硬件，修改引脚配置和逻辑可控制。(EEPROM project, the realization of the basic reading and writing for reference. The IDE used in the project is "ISE Design Suite 14.7", which can be used to modify pin configuration and logic control according to its own hardware.)
Platform: | Size: 159744 | Author: shaoyang_v | Hits:

[VHDL-FPGA-Verilog] uart_test_Verilog

Description: 用verilog实现了uart功能的demo工程。工程使用的IDE为“ISE Design Suite 14.7”，使用时可根据自己硬件，修改引脚配置即可。(The demo project of UART function is realized with Verilog. The IDE used in the project is "ISE Design Suite 14.7", which can be used to modify the pin configuration according to its own hardware.)
Platform: | Size: 128000 | Author: shaoyang_v | Hits:

[VHDL-FPGA-Verilog] microblaze实例教程

Description: 一般而言，Xilinx Microblaze会被用来在系统中做一些控制类和简单接口的辅助性工作，比如运行IIC、SPI、UART之类的低速接口驱动，对FPGA逻辑功能模块初始化配置及做些辅助计算等等。类程序的代码量普遍不大，常常在十几KB到几时KB之间，因此对存储的需求通常也不是太高，使用FPGA内部RAM资源便已经够用(Generally speaking, Xilinx Microblaze will be used to do some auxiliary work of control class and simple interface in the system, such as running low-speed interface driver such as IIC, SPI and UART, initializing configuration of FPGA logic function module and doing auxiliary calculation. The amount of code of class programs is generally not large, often between KB and KB, so the demand for storage is usually not too high. The use of FPGA internal RAM resources is enough.)
Platform: | Size: 26932224 | Author: 叮咯咙咚呛36 | Hits:

[VHDL-FPGA-Verilog] 图像中值滤波FPGA实现V1.0

Description: 实现图像的中值滤波功能，文件里有效果展示(The realization of the median filter function of the image, the file has the effect of display)
Platform: | Size: 30031872 | Author: gxgone | Hits:

[VHDL-FPGA-Verilog] 3-8译码器VHDL描述

Description: 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4；利用XIlinX编程，使用VHDL语言来描述组合逻辑器件3-8译码器(In the FPGA:Spartan-3E development board series, XC3S500E, FGT320, -4 package: speed; the use of XIlinX programming, using VHDL language to describe the combination of the 3-8 decoder logic device)
Platform: | Size: 10240 | Author: lixilin | Hits:

[VHDL-FPGA-Verilog] 可逆计数器VHDL描述

Description: 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4，利用Xilinx ISE软件，利用VHDL软件编写可逆计数器，包含实验说明以及代码实现VHDL.doc文件,UCF管脚绑定文件(In the FPGA:Spartan-3E development board series, XC3S500E, package: FGT320, speed -4, using Xilinx ISE software, written in a reversible counter by using VHDL software, including experimental description and code to achieve the VHDL.doc file, the UCF pin binding file)
Platform: | Size: 12288 | Author: lixilin | Hits:

[VHDL-FPGA-Verilog] 按键去抖电路VHDL描述

Description: 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4，利用Xilinx ISE软件，利用VHDL软件编写按键去抖电路，包含实验说明以及代码实现VHDL.doc文件,UCF管脚绑定文件(In the FPGA:Spartan-3E development board series, XC3S500E, package: FGT320, speed -4, using Xilinx ISE software, write the debounce circuit by using VHDL software, including experimental description and code to achieve the VHDL.doc file, the UCF pin binding file)
Platform: | Size: 29696 | Author: lixilin | Hits:

[VHDL-FPGA-Verilog] vga_test

Description: 用黑金板AX309实现对VGA口的控制，驱动显示器显示。程序基于ISE14.7，语言为Verilog。实测可用。(The black gold board AX309 realizes the control of the VGA port and drives the display of the display. The program is based on ISE14.7 and the language is Verilog. Measured available.)
Platform: | Size: 851968 | Author: 曹玄德 | Hits:

[VHDL-FPGA-Verilog] lmf

Description: 在ISE下，FPGA产生线性调频信号，并且产生信号的参数可调(In ISE, the FPGA generates a linear frequency modulation signal, and the parameters of the signal are adjustable.)
Platform: | Size: 1484800 | Author: QAQ取啥啥不行 | Hits:

[VHDL-FPGA-Verilog] BPSK

Description: 先用Matlab理论仿真，得出滤波器系数。再用Verilog语言在ISE环境下编写程序，通过Modelsim和ChipScope进行波形仿真和引号抓取，从而提高调试的效率。通过手机发送指令来控制上下变频器的参数。(Firstly, the filter coefficients are obtained by simulation with the theory of matlab. Then the program is written in Verilog language under ISE environment. Waveform simulation and quotation mark grabbing are carried out through Modelsim and ChipScope, so as to improve the efficiency of debugging. The parameters of up-down converter are controlled by sending instructions from mobile phone.)
Platform: | Size: 6740992 | Author: 财哥在此 | Hits:
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